Hironori Kasahara is a Senior Executive Vice President at Waseda University. He was a president in 2018 and a member of Executive Committee from 2017 trough 2019, Board of Governors from 2009 through 2014 at IEEE Computer Society. He is an IEEE Fellow, an IPSJ Fellow, a Golden Core Member of the IEEE Computer Society, a professional member of the IEEE Eta Kappa Nu, and a member of the Engineering Academy of Japan and the Science Council of Japan. He received a PhD in 1985 from Waseda University, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at the University of California, Berkeley, and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D.He has served as a chair or member of 250 society and government committees, including a member of the CS Board of Governors and Executive Committee; chair of CS Planing Committee, Constitution & Bylaws Committee, Multicore STC, and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, and ASPLOS; board member of IEEE Tokyo section; and member of the Earth Simulator and K supercomputer committees. Kasahara received Spirit of IEEE Computer Society Award. CS Golden Core Member Award, IFAC World Congress Young Author Prize, Sakai Special Research Award, and the Japanese Minister’s Science and Technology Prize. He led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 218 papers, 186 invited talks, and 52 patents. His research has appeared in 615 newspaper and web articles.


Hironori Kasahara
Waseda University
2018 IEEE Computer Society President

Green Multicore Computing

Power reduction of computing systems, including the World’s Top HPC systems consuming more than 20MW, data centers using LLM consuming 100MW, PCs, smartphones, self-driving vehicles, and AI robots, is crucial for the long-term reliable use of cars and robots with AI and sustainable society. This keynote introduces the codesign of multicore software and hardware and their execution performance and power consumption. All the above computing systems use homogenous multicore and heterogeneous multicore processors with accelerators and “BIG, or Performance” and “LITTLE, or Efficient” cores. MPI and OpenMP are used for parallel programming for those systems to get higher performance using users’ knowledge. However, limited experienced users can obtain the best performance with long-term tuning of accelerators, caches, shared memories, local memories, synchronizations, communications, and load distribution. Also, there are no successful examples of user programs reducing the power consumption of the hardware. The codesigned compiler and hardware allow us to get high performance and low power automatically simultaneously. Those technologies are introduced in this talk.